Single 12-bit ADC (10.25 GSPS) / Dual 16-bit DAC (12.6 GSPS) FMC+モジュール (HiTech Global社)

• High instantaneous dynamic range
  • Noise spectral density 154dBFS/Hz
  • SFDR 68dBc (1GHz, −1dBFS)
• Low power consumption: 5.1W at 10Gsps
• Integrated Input Buffer (6.5GHz input bandwidth)
  • 1.4V p-p full-scale input with RIN=50 Ω
  • Overvoltage protection
• 16-lane JESD204B output (up to 16 Gbps line rate)
• Multichip sync capable with 1 sample accuracy
  • DDC NCO synchronization included
• Fast overrange detection for efficient AGC
• Integrated DDC
  • Selectable decimation factors
  • 16-profile settings for fast frequency hopping
• Optional on-chip PLL clock multiplier
• On-chip temperature sensor
• On-chip negative voltage generators
• Low CER <1e−16 

Applications:

• Supports multiband wireless applications
  • 3 bypassable, complex data input channels per RF DAC
  • 1.54 GSPS maximum complex input data rate per input channel
  • 1 independent NCO per input channel
• Proprietary, low spurious and distortion design
  • 2-tone intermodulation distortion (IMD) = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
  • Spurious free dynamic range (SFDR) <−80 dBc at 1.8 GHz, −7 dBFS RF output
• Flexible 8-lane, 15.4 Gbps JESD204B interface
  • Supports single-band and multiband use cases
  • Supports 12-bit high density mode for increased data throughput
• Multiple chip synchronization
  • Supports JESD204B Subclass 1
• Selectable interpolation filter for a complete set of input data rates
  • 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation
  • 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation
• Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz
• Transmit enable function allows extra power saving and downstream circuitry protection
• High performance, low noise PLL clock multiplier
  • Supports 12.6 GSPS DAC update rate
  • Observation ADC clock driver with selectable divide ratios
• Low power
  • 2.55 W at 12 GSPS, dual channel mode

Applications: